“Writing” or “erasing” a flash memory cell corresponds to shifting the threshold voltage (Vt) of the cell up or down in relation to the reading voltage applied to the gate of the cell. For example, using a read voltage of 5.0 V, the cell is considered erased if its Vt is 4.0 V or less (with a 1.0 V erase margin). The cell is considered written when its Vt is shifted to 6.0V or more (with a 1.0 V write margin). The margin is necessary because the cell may slightly change its Vt when it is cycled with multiple write/erase operations (assuming fixed length and numbers of write/erase pulses), or it may simply change over time during storage. The Vt increase of an erased cell is dubbed “data gain” while the Vt decrease of a written cell is dubbed “data loss.” Usually chips are erased before being shipped to the customer. A small data gain/data loss is typical for flash memory technology and it can be tolerated. Excessive data gain and data loss may, however, cause errors in reading the flash memory.
Erasing a flash memory with a given margin against data gain requires a complex algorithm. The flash memory chips usually contain internal circuits to erase single blocks of memory cells, then the entire memory, with a specified erase margin. The full internal erase-erase check algorithm involves many steps such as Pre-program, Pre-program Verify, Erase Verify, Erase, Depletion check, Compaction, Erase Verify. The Erase Verify step checks that all cells are erased with a desired margin. If the Erase Verify does not give the expected result, the chip will cycle over some of the above steps. Consequently, the overall erase-erase check operation is quite long. For example, for a 32M flash, it may take up to 20 seconds on flash memory test equipment, which may be up to 40% of the total test time. Even more time is needed for larger memories.
It is possible to erase the memory without making use of the internal algorithm, by using a simplified external erase algorithm with parameters specified by the flash test equipment. This is normally done by flash manufacturers at the time of the product final test. The external algorithm does not perform complex cycles, avoiding increased testing time. In most cases, the external algorithm used at final test is sufficient for a good erase. However, a few cells in some memory chips may be imperfectly erased and thus be more susceptible to data gain. With the external algorithm, it is not guaranteed that all of the chips will be erased with an adequate safety margin. Some chips, particularly those that have been in storage for a long period of time will be subject to data gain. The customer can follow three possible strategies to write data into flash memories on the production line:                1) The customer can assume that the flash memory chip is completely erased and proceed to write data into the memory without any prior check. In this case the customer does not spend time to perform erase checks but if the memory is not completely erased there can be errors in the data written or if the memory has no safe erase margins there may be future data corruption due to data gain or disturbance.        2) The customer can perform a regular read of the entire block and see if it is erased before writing new data. This regular read is not a background operation, it can only be performed location by location. Furthermore, a regular read can only be performed at a fixed reference value (typically 5V) and no safety data retention margins are guaranteed. The customer spends time for this regular read and still risks future data corruption.        3) The customer can perform a regular erase before writing. In this case, the customer can be sure that the block is erased with safe margins but this is a time consuming operation that has a cost. It would thus be desirable to provide a more efficient method of ensuring that flash memory are completely erased to adequate safety margins before they are installed by customers.        